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never stop thinking. hys64d64020gbdl?5?b hys64d64020gbdl?6?b hys64d64020gbdl?7?b hys64d64020gbdl?8?b 200-pin small outline dual-in-line memory modules so-dimm ddr sdram data sheet, v1.0, aug. 2003 memory products
edition 2003-08 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hys64d64020gbdl?5?b hys64d64020gbdl?6?b hys64d64020gbdl?7?b hys64d64020gbdl?8?b 200-pin small outline dual-in-line memory modules so-dimm ddr sdram data sheet, v1.0, aug. 2003 memory products
template: mp_a4_v2.0_2003-06-06.fm hys64d64020gbdl?5?b, hys64d64020gbdl?6?b, hys64d64020gbdl?7?b, hys64d64020gbdl?8?b revision history: v1.0 2003-08 previous version: 0.6 2003-03 page subjects (major changes since last revision) all new data sheet template 21 changed spd programming byte tqhs for bga package from 0.6ns to 0.5ns (scr-050) 16 editorial change: tqhs set to 0.5ns in electrical characteristics, and tdqsq to 0.4ns 6 , 7 , 15 , 21 added ddr 400 15 updated idd currents we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
data sheet 5 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 current specification and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 5 spd contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table of contents
data sheet 6 v1.0, 2003-08 200-pin small outline dual-in-line memory modules so-dimm hys64d64020gbdl?5?b hys64d64020gbdl?6?b hys64d64020gbdl?7?b hys64d64020gbdl?8?b 1 overview 1.1 features non-parity 200-pin small outline dual-in-line memory modules two ranks 64m 64 organization jedec standard double data rate synchronous drams (ddr sdram) single +2.5v ( 0.2 v) power supply built with 256 mbit ddr sdrams organised as 8 in p?fbga?60?1 packages programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs and outputs sstl_2 compatible serial presence detect with e 2 prom jedec standard form factor: 67.60 mm 31.75 mm 3.80 mm gold plated contacts 1.2 description the hys64d64020gbdl?[5/6/7/8]?b are industry standard 200-pin small outline dual-in-line memory modules (so-dimms) organized 64m 64. the memory array is designed with double data rate synchronous drams (ddr sdram). a variety of decoupling capacitors are mounted on the pc board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. table 1 performance part number speed code ?5 ? 6 ? 7 ? 8unit speed grade component ddr400b ddr333b ddr266a ddr200 ? module pc3200?3033 pc2700?2533 pc2100?2033 pc1600?2022 ? max. clock frequency @cl3 f ck3 200 166 ? ? mhz @cl2.5 f ck2.5 166 166 143 125 mhz @cl2 f ck2 133 133 133 100 mhz
data sheet 7 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules overview notes 1. all part numbers end with a place code designating the silicon-die revision. reference information available on request. example: hys64d32020gdl-6-b, indicating rev. b dies are used for sdram components. 2. the compliance code is printed on the module labels describing the speed sort (for example ?pc2700?), the latencies and spd code definition (for example ?2033 ? 0? means cas latency of 2.0 clocks, rcd 1) latency of 3 clocks, row precharge latency of 3 clocks, and jedec spd code definiton version 0), and the raw card used for this module. table 2 ordering information type compliance code description sdram technology pc3200 (cl=3) hys64d64020gbdl-5-b pc3200s?3033?0?z two ranks 512 mb so-dimm 256 mbit ( 8) pc2700 (cl=2,5) hys64d64020gbdl-6-b pc2700s-2533-0-z two ranks 512 mb so-dimm 256 mbit ( 8) pc2100 (cl=2) HYS64D64020GBDL-7-B pc2100s-2033-0-z two ranks 512 mb so-dimm 256 mbit ( 8) pc1600 (cl=2) hys64d64020gbdl-8-b pc1600s-2022-0-z two ranks 512 mb so-dimm 256 mbit ( 8) 1) rcd: row-column-delay
hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules pin configuration data sheet 8 v1.0, 2003-08 2 pin configuration table 3 pin definitions and functions symbol type 1) 1) i: input; o: output; i/o: bidirectional in-/output; ai: analog input; pwr: power supply; gnd: signal ground; nc: not connected; nu: not usable function a0 - a12 i address inputs ba0, ba1 i bank address dq0 - dq63 i/o data input/output ras , cas , we i command input cke0 - cke1 i clock enable dqs0 - dqs7 i/o sdram data strobe ck0 - ck1, i sdram clock (true signal) ck0 - ck1 i sdram clock (complementary signal) dm0 - dm8 i data mask s0 , s1 2) 2) cke1 and s1 are used on two bank modules only ichip select v dd pwr power (+ 2.5 v) v ss gnd ground v ddq pwr i/o driver power supply v ddid pwr vdd indentification flag v ref ai i/o reference supply v ddspd pwr serial eeprom power supply scl i serial bus clock sda i/o serial bus data line sa0 - sa2 i slave address select nc nc not connected nu nu not usable, reserved for future use table 4 address format density organization memory ranks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 512mb 64m 64 2 32m 8 16 13/2/10 8k 64 ms 7.8 s
data sheet 9 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules pin configuration table 5 pin configuration front side back side front side back side front side back side pin # symbol pin # symbol pin # symbol pin # symbol pin # symbol pin # symbol 1 v ref 2 v ref 65 dq26 66 dq30 133 dqs4 134 dm4 3 v ss 4 v ss 67 dq27 68 dq31 135 dq34 136 dq38 5 dq0 6 dq4 69 v dd 70 v dd 137 v ss 138 v ss 7 dq1 8 dq5 71 (cb0) 72 (cb4) 139 dq35 140 dq39 9 v dd 10 v dd 73 (cb1) 74 (cb5) 141 dq40 142 dq44 11 dqs0 12 dm0 75 v ss 76 v ss 143 v dd 144 v dd 13 dq2 14 dq6 77 (dqs8) 78 (dm8) 145 dq41 146 dq45 15 v ss 16 v ss 79 (cb2) 80 (cb6) 147 dqs5 148 dm5 17 dq3 18 dq7 81 v dd 82 v dd 149 v ss 150 v ss 19 dq8 20 dq12 83 (cb3) 84 (cb7) 151 dq42 152 dq46 21 v dd 22 v dd 85 du 86 du 153 dq43 154 dq47 23 dq9 24 dq13 87 v ss 88 v ss 155 v dd 156 v dd 25 dqs1 26 dm1 89 (ck2) 90 v ss 157 v dd 158 ck1 27 v ss 28 v ss 91 (ck2) 92 v dd 159 v ss 160 ck1 29 dq10 30 dq14 93 v dd 94 v dd 161 v ss 162 v ss 31 dq11 32 dq15 95 cke1 96 cke0 163 dq48 164 dq52 33 v dd 34 v dd 97 du 98 du 165 dq49 166 dq53 35 ck0 36 v dd 99 a12 100 a11 167 v dd 168 v dd 37 ck0 38 v ss 101 a9 102 a8 169 dqs6 170 dm6 39 v ss 40 v ss 103 v ss 104 v ss 171 dq50 172 dq54 key 105 a7 106 a6 173 v ss 174 v ss 107 a5 108 a4 175 dq51 176 dq55 41 dq16 42 dq20 109 a3 110 a2 177 dq56 178 dq60 43 dq17 44 dq21 111 a1 112 a0 179 v dd 180 v dd 45 v dd 46 v dd 113 v dd 114 v dd 181 dq57 182 dq61 47 dqs2 48 dm2 115 a10/ap 116 ba1 183 dqs7 184 dm7 49 dq18 50 dq22 117 ba0 118 ras 185 v ss 186 v ss 51 v ss 52 v ss 119 we 120 cas 187 dq58 188 dq62 53 dq19 54 dq23 121 s0 122 s1 189 dq59 190 dq63 55 dq24 56 dq28 123 du 124 du 191 v dd 192 v dd 57 v dd 58 v dd 125 v ss 126 v ss 193 sda 194 sa0 59 dq25 60 dq29 127 dq32 128 dq36 195 scl 196 sa1 61 dqs3 62 dm3 129 dq33 130 dq37 197 v ddspd 198 sa2 63 v ss 64 v ss 131 v dd 132 v dd 199 v ddid 200 du
hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules pin configuration data sheet 10 v1.0, 2003-08 figure 1 pin configuration pin 1 pin 39 pin 41 pin 199 pin 2 pin 40 pin 42 pin 200 front side back side
data sheet 11 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules pin configuration dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 dm d8 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 dm d9 i/o 4 i/o 5 i/o 6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 dm d10 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 dm d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 dm d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 dm d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 dm d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 dm d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm7/dqs16 a0 - a13 a0-a13: sdrams d0 - d15 a0 serial pd a1 a2 sa0 sa1 sa2 sda ras ras : sdrams d0 - d15 cas cas : sdrams d0 - d15 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d15 s 0 s 1 s s s s s s s s s s s s s s s s cke1 cke: sdrams d8 - d15 ba0 - ba1 ba0-ba1: sdrams d0 - d15 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 7 i/o 7 dqs dqs dqs dqs dqs dqs dqs dqs dqs * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 4 sdrams 6 sdrams 6 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 v ss d0 - d15 v dd /v ddq d0 - d15 d0 - d15 v ref v ddid strap: see note 4 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms 5%. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq 5. bax, ax, ras , cas , we resistors: 3 ohms + 5% scl wp spd v dd spd figure 2 block diagram - two rank 64m 64 ddr sdram so-dimm hys64d64020gbdl?[5/6/7/8]?b
data sheet 12 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules electrical characteristics 3 electrical characteristics 3.1 operating conditions attention: permanent damage to the device may occur if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be restricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. table 6 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) p d ?1?w? short circuit output current i out ?50?ma? table 7 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck >166mhz 2) output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) eeprom supply voltage v ddspd 2.3 2.5 3.6 v ? supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4) i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 5) input high (logic1) voltage v ih(dc) v ref + 0.15 v ddq + 0.3 v 8) input low (logic0) voltage v il(dc) ?0.3 v ref ? 0.15 v 8) input voltage level, ck and ck inputs v in(dc) ?0.3 v ddq + 0.3 v 8) input differential voltage, ck and ck inputs v id(dc) 0.36 v ddq + 0.6 v 8)6) vi-matching pull-up current to pull-down current vi ratio 0.71 1.4 ? 7)
data sheet 13 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules electrical characteristics input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test =0v 8)9) output leakage current i oz ?5 5 a dqs are disabled; 0v v out v ddq 8) output high current, normal strength driver i oh ??16.2ma v out = 1.95 v 8) output low current, normal strength driver i ol 16.2 ? ma v out = 0.35 v 8) 1) 0 c t a 70 c 2) ddr400 conditions apply for all clock frequencies above 166 mhz 3) under all conditions, v ddq must be less than or equal to v dd . 4) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . 5) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 6) v id is the magnitude of the difference between the input level on ck and the input level on ck . 7) the ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 v. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) inputs are not recognized as valid until v ref stabilizes. 9) values are shown per ddr sdram component table 7 electrical characteristics and dc operating conditions (cont?d) parameter symbol values unit note/test condition 1) min. typ. max.
data sheet 14 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules electrical characteristics 3.2 current specification and conditions table 8 i dd conditions parameter symbol operating current 0 one bank; active/ precharge; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. i dd0 operating current 1 one bank; active/read/precharge; burst length = 4; see component data sheet. i dd1 precharge power-down standby current all banks idle; power-down mode; cke v il,max i dd2p precharge floating standby current cs v ih,min , all banks idle; cke v ih,min ; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current cs v ih,min , all banks idle; cke v ih,min ; v in = v ref for dq, dqs and dm; address and other control inputs stable at v ih,min or v il,max . i dd2q active power-down standby current one bank active; power-down mode; cke v ilmax ; v in = v ref for dq, dqs and dm. i dd3p active standby current one bank active; cs v ih,min ; cke v ih,min ; t rc = t ras,max ; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. i dd3n operating current read one bank active; burst length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b; i out =0ma i dd4r operating current write one bank active; burst length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b i dd4w auto-refresh current t rc = t rfcmin , burst refresh i dd5 self-refresh current cke 0.2 v; external clock on i dd6 operating current 7 four bank interleaving with burst length = 4; see component data sheet. i dd7
data sheet 15 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules electrical characteristics table 9 i dd specification part number & organization hys64d64020gbdl?5?b hys64d64020gbdl?6?b hys64d64020gbdl?7?b hys64d64020gbdl?8?b unit note 1)2) 1) dram component currents only 2) test condition for maximum values: v dd =2.7v, t a =10c 512 mb 512 mb 512 mb 512 mb 64 64 64 64 2 ranks 2 ranks 2 ranks 2 ranks ?5 ?6 ?7 ?8 symbol typ. max. typ. max. typ. max. typ. max. i dd0 1280 1552 1208 1480 1032 1320 912 1160 ma 3) 3) the module i ddx values are calculated from the component i ddx data sheet values as: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 1400 1672 1336 1560 1168 1400 1000 1240 ma 3)4) 4) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured differently depending on load conditions i dd2p 96 144 96 144 88 128 80 112 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 736 896 720 880 560 640 480 560 ma 5) i dd2q 384 544 395 448 320 400 288 352 ma 5) i dd3p 272 384 288 336 240 288 208 256 ma 5) i dd3n 960 1184 1008 1120 832 960 672 800 ma 5) i dd4r 1600 1992 1496 1840 1272 1520 1048 1280 ma 3)4) i dd4w 1680 2032 1632 1880 1368 1600 1104 1360 ma 3) i dd5 1720 2152 1652 2080 1496 1920 1346 1760 ma 3) i dd6 21 38 20 36 20 36 20 36 ma 5) i dd7 2560 3072 2248 2840 1856 2360 1600 2160 ma 3)4)
data sheet 16 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules ac characteristics 4 ac characteristics table 10 ac timing - absolute specifications ?8/?7 parameter symbol ?8 ?7 unit note/ test conditio n 1) ddr200 ddr266a min. max. min. max. dq output access time from ck/ck t ac ?0.8 +0.8 ?0.75 +0.75 ns 2)3)4)5) dqs output access time from ck/ck t dqsck ?0.8 +0.8 ?0.75 +0.75 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )ns 2)3)4)5) clock cycle time t ck3 8 12 7 12 ns cl = 3.0 2)3)4)5) t ck2.5 8 12 7 12 ns cl = 2.5 2)3)4)5) t ck2 10 12 7.5 12 ns cl = 2.0 2)3)4)5) t ck1.5 10 12 ? ? ns cl = 1.5 2)3)4)5) dq and dm input hold time t dh 0.6 ? 0.5 ? ns 2)3)4)5) dq and dm input setup time t ds 0.6 ? 0.5 ? ns 2)3)4)5) control and addr. input pulse width (each input) t ipw 2.5 ? 2.2 ? ns 2)3)4)5)6) dq and dm input pulse width (each input) t dipw 2.0 ? 1.75 ? ns 2)3)4)5)6) data-out high-impedance time from ck/ck t hz ?0.8 +0.8 ?0.75 +0.75 ns 2)3)4)5)7) data-out low-impedance time from ck/ck t lz ?0.8 +0.8 ?0.75 +0.75 ns 2)3)4)5)7) write command to 1 st dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.6 ? +0.5 ns tfbga 2)3)4)5) data hold skew factor t qhs ? 1.0 ? 0.75 ns tfbga 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs ? t hp ? t qhs ?ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) mode register set command cycle time t mrd 2? 2 ? t ck 2)3)4)5) write preamble setup time t wpres 0? 0 ? ns 2)3)4)5)8) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)9) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) address and control input setup time t is 1.1 ? 0.9 ? ns fast slew rate 3)4)5)6)10) 1.1 ? 1.0 ? ns slow slew rate 3)4)5)6)10) address and control input hold time t ih 1.1 ? 0.9 ? ns fast slew rate 3)4)5)6)10) 1.1 ? 1.0 ? ns slow slew rate 3)4)5)6)10)
data sheet 17 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules ac characteristics read preamble t rpre 0.9 1.1 0.9 1.1 t ck cl > 1.5 2)3)4)5) t rpre1.5 0.9 1.1 na t ck cl = 1.5 2)3)4)5)11) read preamble setup time t rpres 1.5 ? na ns 2)3)4)5)12) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active to precharge command t ras 50 120e+3 45 120e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 70 ? 65 ? ns 2)3)4)5) auto-refresh to active/auto-refresh command period t rfc 80 ? 75 ? ns 2)3)4)5) active to read or write delay t rcd 20 ? 20 ? ns 2)3)4)5) precharge command period t rp 20 ? 20 ? ns 2)3)4)5) active to autoprecharge delay t rap 20 ? 20 ? ns 2)3)4)5) active bank a to active bank b command t rrd 15 ? 15 ? ns 2)3)4)5) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck ) + ( t rp / t ck ) t ck 2)3)4)5)13) internal write to read command delay t wtr 1? 1 ? t ck cl > 1.5 2)3)4)5) t wtr1.5 2? ?? t ck cl = 1.5 2)3)4)5) exit self-refresh to non-read command t xsnr 80 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) average periodic refresh interval t refi ? 7.8 ? 7.8 s 2)3)4)5)14) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v 2) input slew rate 1 v/ns for ddr400, ddr333, ddr266, and = 1 v/ns for ddr200 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) these parameters guarantee device timing, but they are not necessarily tested on each device. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8) the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 9) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ ns, measured between v oh(ac) and v ol(ac) . 11) cas latency 1.5 operation is supported on ddr200 devices only 12) t rpres is defined for cl = 1.5 operation only 13) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 14) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. table 10 ac timing - absolute specifications ?8/?7 (cont?d) parameter symbol ?8 ?7 unit note/ test conditio n 1) ddr200 ddr266a min. max. min. max.
data sheet 18 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules ac characteristics table 11 ac timing - absolute specifications ?6/?5 parameter symbol ?6 ?5 unit note/ test condition 1) ddr333 ddr400b min. max. min. max. dq output access time from ck/ck t ac ?0.7 +0.7 ?0.6 +0.6 ns 2)3)4)5) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.5 +0.5 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )ns 2)3)4)5) clock cycle time t ck 6 12 5 12 ns cl = 3.0 2)3)4)5) 6 12 6 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) dq and dm input hold time t dh 0.45 ? 0.4 ? ns 2)3)4)5) dq and dm input setup time t ds 0.45 ? 0.4 ? ns 2)3)4)5) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)6) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5)6) data-out high-impedance time from ck/ck t hz ?0.7 +0.7 ?0.6 +0.6 ns 2)3)4)5)7) data-out low-impedance time from ck/ ck t lz ?0.7 +0.7 ?0.6 +0.6 ns 2)3)4)5)7) write command to 1 st dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.40 ns tfbga 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.50 ns tfbga 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs ? t hp ? t qhs ?ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) mode register set command cycle time t mrd 2?2? t ck 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)8) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)9) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5)
data sheet 19 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules ac characteristics address and control input setup time t is 0.75 ? 0.6 ? ns fast slew rate 3)4)5)6)10) 0.8 ? 0.7 ? ns slow slew rate 3)4)5)6)10) address and control input hold time t ih 0.75 ? 0.6 ? ns fast slew rate 3)4)5)6)10) 0.8 ? 0.7 ? ns slow slew rate 3)4)5)6)10) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active to precharge command t ras 42 70e+3 40 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 60 ? 55 ? ns 2)3)4)5) auto-refresh to active/auto-refresh command period t rfc 72 ? 65 ? ns 2)3)4)5) active to read or write delay t rcd 18 ? 15 ? ns 2)3)4)5) precharge command period t rp 18 ? 15 ? ns 2)3)4)5) active to autoprecharge delay t rap 18 ? 15 ? ns 2)3)4)5) active bank a to active bank b command t rrd 12 ? 10 ? ns 2)3)4)5) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) auto precharge write recovery + precharge time t dal t ck 2)3)4)5)11) internal write to read command delay t wtr 1?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) average periodic refresh interval t refi ?7.8 ?7.8 s 2)3)4)5)12) 1) 0 c t a 70 c ; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) these parameters guarantee device timing, but they are not necessarily tested on each device. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8) the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . table 11 ac timing - absolute specifications ?6/?5 (cont?d) parameter symbol ?6 ?5 unit note/ test condition 1) ddr333 ddr400b min. max. min. max.
data sheet 20 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules ac characteristics 9) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ ns, measured between v oh(ac) and v ol(ac) . 11) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 12) a maximum of eight autorefresh commands can be posted to any given ddr sdram device.
hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules spd contents data sheet 21 v1.0, 2003-08 5 spd contents table 12 spd codes for hys64d64020gbdl?[5/6/7/8]?b part number & organization hys64d64020gbdl?5?b hys64d64020gbdl?6?b hys64d64020gbdl?7?b hys64d64020gbdl?8?b 512 mb 512 mb 512 mb 512 mb 64 64 64 64 2 ranks 2 ranks 2 ranks 2 ranks ?5 ?6 ?7 ?8 byte# description hex hex hex hex 0 programmed spd bytes in e2prom 80 80 80 80 1 total number of bytes in e2prom 08 08 08 08 2 memory type ddr-i = 07h 07 07 07 07 3 # of row addresses 0d 0d 0d 0d 4 # number of column addresses 0a 0a 0a 0a 5 # of dimm banks 02 02 02 02 6 data width (lsb) 40 40 40 40 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 tck @ clmax (byte 18) [ns] 50 60 70 80 10 tac sdram @ clmax (byte 18) [ns] 50 70 75 80 11 dimm configuration type (non- / ecc) 00 00 00 00 12 refresh rate 82 82 82 82 13 primary sdram width 08 08 08 08 14 error checking sdram width 00 00 00 00 15 tccd [cycles] 01 01 01 01 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram 04 04 04 04 18 cas latency 1c 0c 0c 0c 19 cs latency 01 01 01 01 20 we (write) latency 02 02 02 02 21 dimm attributes 20 20 20 20 22 component attributes c1 c1 c1 c1 23 tck @ clmax -0.5 (byte 18) [ns] 60 75 75 a0 24 tac sdram @ clmax -0.5 [ns] 50 70 75 80 25 tck @ clmax -1 (byte 18) [ns] 75 00 00 00 26 tac sdram @ clmax -1 [ns] 50 00 00 00 27 trpmin (ns) 3c 48 50 50
data sheet 22 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules spd contents 28 trrdmin [ns] 28 30 3c 3c 29 trcdmin [ns] 3c 48 50 50 30 trasmin [ns] 28 2a 2d 32 31 module density per bank 40 40 40 40 32 tas, tcs [ns] 60 75 90 b0 33 tah, tch [ns] 60 75 90 b0 34 tds [ns] 40 45 50 60 35 tdh [ns] 40 45 50 60 36 - 40 not used 00 00 00 00 41 trcmin [ns] 37 3c 41 46 42 trfcmin [ns] 41 48 4b 50 43 tckmax [ns] 28 30 30 30 44 tdqsqmax [ns] 28 28 32 3c 45 tqhsmax [ns] 50 50 75 a0 46 - 61 not used 00 00 00 00 62 spd revision 00 00 00 00 63 checksum of byte 0-62 (lsb only) fe f8 b4 a9 64 jedec id code for infineon c1 c1 c1 c1 65 jedec id code for infineon 49 49 49 49 66 jedec id code for infineon 4e 4e 4e 4e 67 jedec id code for infineon 46 46 46 46 68 jedec id code for infineon 49 49 49 49 69 jedec id code for infineon 4e 4e 4e 4e 70 jedec id code for infineon 45 45 45 45 71 jedec id code for infineon 4f 4f 4f 4f 72 module manufacturer location xx xx xx xx 73 part number, char 1 36 36 36 36 74 part number, char 2 34 34 34 34 75 part number, char 3 44 44 44 44 table 12 spd codes for hys64d64020gbdl?[5/6/7/8]?b part number & organization hys64d64020gbdl?5?b hys64d64020gbdl?6?b hys64d64020gbdl?7?b hys64d64020gbdl?8?b 512 mb 512 mb 512 mb 512 mb 64 64 64 64 2 ranks 2 ranks 2 ranks 2 ranks ?5 ?6 ?7 ?8 byte# description hex hex hex hex
hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules spd contents data sheet 23 v1.0, 2003-08 76 part number, char 4 36 36 36 36 77 part number, char 5 34 34 34 34 78 part number, char 6 30 30 30 30 79 part number, char 7 32 32 32 32 80 part number, char 8 30 30 30 30 81 part number, char 9 47 47 47 47 82 part number, char 10 42 42 42 42 83 part number, char 11 44 44 44 44 84 part number, char 12 4c 4c 4c 4c 85 part number, char 13 35 36 37 38 86 part number, char 14 42 42 42 42 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 90 part number, char 18 20 20 20 20 91 module revision code xx xx xx xx 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 table 12 spd codes for hys64d64020gbdl?[5/6/7/8]?b part number & organization hys64d64020gbdl?5?b hys64d64020gbdl?6?b hys64d64020gbdl?7?b hys64d64020gbdl?8?b 512 mb 512 mb 512 mb 512 mb 64 64 64 64 2 ranks 2 ranks 2 ranks 2 ranks ?5 ?6 ?7 ?8 byte# description hex hex hex hex
data sheet 24 v1.0, 2003-08 hys64d64020gbdl?[5/6/7/8]?b small outline ddr sdram modules package outlines 6 package outlines figure 3 package outlines ? ddr-sdram so-dimm hys64d64020gbdl?[5/6/7/8]?b l-dim-200-006 0.1 63.6 67.6 31.75 0.1 4 1 0.1 18.45 1.8 0.1 11.4 0.1 (2.4) 47.4 0.1 63 0.1 1 4 0.1 0.1 0.1 1.5 (2.7) 2 min. 0.1 20 0.1 6 3.8 max. 1 0.1 0.15 burnished, no burr allowed 0.1 0.6 0.03 0.45 detail of contacts -0.18 0.25 2.55 (2.15) (2.45) 0.05 1.8 (2.15) (2.45) 100 200 101
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